1. Field of the Invention
The present invention relates to a driving circuit for a liquid crystal display device suitable for driving a fast response type liquid crystal display element. In particular, the present invention relates to a driving circuit suitable for a liquid crystal display device driven by a multiple line selection method.
2. Discussion of the Background
A STN liquid crystal element is a liquid crystal display element responsive depending on the root mean squared (RMS) value of an applied voltage. In the liquid crystal display element, when a STN liquid crystal display element of a fast responsive type is used, a so-called frame response wherein an optical change between an ON state and an OFF state becomes small to reduce the contrast ratios takes place. Accordingly, when a line successive selection method is used to drive the liquid display element, there is a limit to drive the STN liquid crystal element at a high speed.
Accordingly, in order to the drive the STN liquid crystal element at a higher speed, a multiple line selection method (MLS method) has been proposed. The multiple line selection method is a method of driving a plurality of scanning electrodes (row electrodes) simultaneously. In the multiple line selection method, a predetermined pulse train is applied to each of the simultaneously driven row electrodes in order to control independently a column display pattern to be applied to data electrodes (column electrodes).
A voltage pulse group (a selection pulse group) applied to each of the row electrodes can be expressed by a matrix of L-row.multidot.K-column. Hereinafter, the matrix is referred to as a selection matrix (A) wherein L represents a number simultaneously selected. The voltage pulse group can be expressed by a group of vectors which are mutually orthogonal. Accordingly, a matrix including these vectors as elements is an orthogonal matrix. Each of the column vectors in the matrix is mutually orthogonal. In the orthogonal matrix, each row corresponds to each line in the liquid crystal display element. For instance, the first line in an L number of selection lines corresponds to the elements of the first row in the selection matrix (A). Namely, the first row electrode is applied with selection pulses of the elements of first row, the elements of second row . . . in this order.
FIG. 14 is a diagram showing a sequence of voltage waveforms applied to column electrodes. In FIG. 14, an Hadamard's matrix of 4 row.multidot.4 column is used for the selection matrix (A). In the selection matrix (A) in FIG. 14, "1" indicates a positive selection pulse and "-1" indicates a negative selection pulse.
Supposing that display data on column electrodes i and j are as shown in FIG. 14a, a column display pattern can be expressed as a vector d as shown in FIG. 14b. In FIG. 14b, a numerical value "-1" corresponds to an ON display and "1" corresponds to an OFF display pattern. Voltage patterns successively applied to the column electrodes i, j have vectors v as shown in FIG. 14b. These vectors correspond to sums as a result of an exclusive OR operation for each bit in a column display pattern (a picture display pattern) and a row selection pattern corresponding thereto. The waveform of the vectors is shown in FIG. 14c. In FIG. 14c, the ordinate represents voltage applied to the column electrodes and the abscissa represents time wherein each unit is arbitrary.
When a liquid crystal display element is driven by a multiple line selection methods it is desirable that factors for voltage application be dispersed in a display cycle in order to suppress a frame response of the liquid crystal display element. Specifically, for instance, such a sequence that the first factor of the vectors is applied to the simultaneously selected first row electrode group (hereinbelow, referred to as subgroup), and then, the first factor of the vectors is applied to simultaneously selected second subgroup, is carried out.
Generally, the pulse width of a waveform for driving the liquid crystal display element is determined to be about 10 .mu.sec -- several 10 .mu.sec from the stand point of using a large number of scanning lines and easiness of seeing. Accordingly, a frequency of one display cycle at the liquid crystal display element side is generally about 70-200 Hz. On the other hands a frequency of inputted picture signal is about 60 Hz. Accordingly, it is necessary to adjust a speed of input signal and the speed of signal outputted to the liquid crystal display element side in a liquid crystal driving device.
Such adjustment is generally realized by memories. Namely, the adjustment is realized by writing temporarily input picture image data in the memories, and by reading the written data in an asynchronous manner with respect to the writing operations. For instance, when a frequency of input picture signal is 60 Hz, and a frequency of one display cycle at the liquid crystal element side is 120 Hz, it is necessary that when the data corresponding to a picture are written in the memories, reading of the data from the memories should be done twice. When a multiple line selection method is used, it is necessary to treat K times for a picture image. Accordingly, when data for one picture image are written in the memories, 2K times of reading of the data from the memories has to be carried out.
In the multiple line selection method, the same display data are dispersed in a display frame period and the display data are used plural times. Accordingly, it is necessary to hold the same data for predetermined data periods. Thus, memories are essential. As a quantity of information to be displayed becomes large, a larger number of memories should be used. For a high density display such as VGA, SVGA, XGA and so on, an improved memory control technique is needed.
A conventional memory control technique will be described wherein a frame rate control (FRC) method is employed as a gradation method, and amplitude modulation or pulse width modulation is not used. In the line successive selection method (APT or IAPT) as a conventional driving method for STN, display data for each pixel are used only once in a display frame. Accordingly, when an input frame is in synchronism with an output frame, it is sufficient to display with memories having the capacity as shown in the following Table, and data can be controlled by a simple memory management.
TABLE 1 ______________________________________ Input frame = Input frame = Output frame 2 output frames ______________________________________ Single scan Non 2 picture areas driving Dual scan 1/2 picture areas 1/2 picture areas driving ______________________________________
In this Table, "single scan driving" means a driving method wherein a picture surface is scanned by one continual scanning operation, and "dual scan driving" is a driving method wherein an upper portion and a lower portion of a picture area are scanned by an independent scanning operation respectively. "Input frame=2 output frames" means that one frame for input corresponds to two frames for output wherein output data from the output frame comprises different elements between the two frames due to a FRC graduation treatment In this text, it is also referred to as a double frequency driving.
Generally speaking, in the single scan driving in the line successive driving method, when the length of frames for writing data in memories is formed to be n times (n: a natural number) as large as the length of frames for reading, provision of memories for an n number of picture areas is sufficient for driving. This is because as soon as the data are once read from the memories, the next data can be written in the memories. In particular, when the output frames are in agreement with the input frames, a speed of reading data from the memories agrees with a speed of writing data in the memories. This is a special case which can further save memories corresponding to a picture area. Namely, when the output frames agree with the input frames, memories are unnecessary. Even in this case, however, memories for one picture area are necessary in an asynchronous driving wherein the input frames do not synchronize with the output frames.
In a case of the dual scan driving, a phase of scanning is shifted by half periods between the upper and lower picture areas, and accordingly, memories corresponding to 1/2 picture areas can be saved in comparison with a case of the single picture area driving. In particular, when one frame for input corresponds to two frames for output, the speed of reading data from the memories agrees with the speed of writing. This is a special case which can further same memories for one picture ares, and memories for 1/2 picture areas are sufficient for driving.
On the other hand, since data on respective pixels are used several times (4 times in L=4 and 8 times in L=7) in a frame period in the multiple line selection method. Accordingly, it is impossible to write next data in the memories at the time when the data have just read once from the memories. Accordingly, it is necessary to hold data in order to strictly control the reading and the writing of the data in the memories, and the number of memories is increased in comparison with the conventional driving method.
The quantity of memories required for driving in the multiple line selection method is generally as follows.
In a case of the single scan driving wherein the length of frames for writing data in memories is formed to be n times (n: a natural number) as the length of the frames for reading, driving of the liquid crystal element is possible when n picture areas are prepared for input and output respectively. Namely, 2n picture areas are required.
In a case of the dual scan driving wherein writing is successively conducted on the memories from which data are read out, when n is an odd number, memories corresponding to (n-1)/2 picture areas can be saved, and when n is an even number, memories corresponding to n/2 picture areas can be saved. Supposing that the phase is shifted by 180.degree. between the upper and lower picture areas, and when n is an odd number, memories corresponding to (n+1)/4 picture areas can be saved. On the other hand, when n is an even number, memories corresponding to n/4 picture areas can be saved. In short, the quantity of memories required in the conventional technique is that corresponding to (5n+1)/4 picture areas when n is an odd number, and that corresponding to 5n/4 picture areas when n is an even number.
Accordingly, when the input frames are in synchronism with the output frames, capacities of memories as shown in the following table are required. Namely, a more number of memories is required in comparison with line successive selection method, and a complicated memory control and an increased cost for the circuit are unavoidable. When input frames are not in synchronism with the output frames, a large number of memories is required.
TABLE 2 ______________________________________ Input frame = Input frame = Output frame 2 output frames ______________________________________ Single scan 2 picture areas 4 picture areas driving Dual scan 1.5 picture areas 2.5 picture areas driving ______________________________________
At present, double frequency driving of the dual picture area driving method is used mainly for information devices such as personal computers. In this case, use of memories corresponding to 0.5 picture areas is sufficient for driving when the conventional successive selection method is used. On the other hand, memories corresponding to 2.5 picture areas are necessary for the multiple line selection method. Requirement of 5 times of memory capacity is a big problem in promoting use of the multiple line selection method. Specifically, in a VGA color (640.times.480.times.RGB), an SVGA color (800.times.600.times.RGB) and an XGA color (1024.times.768.times.RGB), memory capacities are required as shown in the following table. It is understood that the multiple line selection method requires a large memory capacity in comparison with the conventional method.
TABLE 3 ______________________________________ VGA SVGA XGA ______________________________________ Line successive 0.5 Mbits 0.7 Mbits 1.2 Mbits selection method Multiple line 2.3 Mbits 3.6 Mbits 5.9 Mbits selection method ______________________________________
FIG. 15 is a block diagram showing a construction of driving circuit 200 for a liquid crystal display device proposed by the inventor in this application in Japanese Unexamined Patent Publication No. 348237/1994. The structure is employed in order to reduce memory capacity as possible in several structures disclosed in Japanese Unexamined Patent Publication No. 348237/1994. The driving circuit operates as described below under the control by a control circuit 150.
As shown in FIG. 15, respective picture image data of R, G and B having graduation information are inputted to a frame modulation circuit 110. The frame modulation circuit 110 converts the inputted picture image data into ON/OFF 1 bit data for each display cycle to output the converted data to a serial-parallel converter 120 which comprises shift resistors and so on. The serial-parallel convertor 120 converts serial data from the frame modulation circuit 110 into parallel data having a predetermined bit width. A memory 130 consisting of VRAM stores picture image data corresponding to one frame. The memory 130 stores data in such a manner that the data of RGB are collected together in a set and each RGB data on an L number of simultaneously selected row electrodes which correspond to a column electrode are set to an L number of continuous addresses. Accordingly, when reading of data is conducted successively from the memory 130 according to an access mode, data corresponding to voltages applied to column drivers 80 are outputted. The data in the memory 130 are outputted to a format converter 190 in synchronism a timing of data input.
The format converter 190 is a circuit for arranging a data format, and conducts a vertical/lateral conversion treatment and so on. The output of the format convertor 190 is supplied to a column voltage signal generator 180. The column voltage signal generator 180 produces voltage values to be applied to column electrodes based on a row selection pattern from a row selection pattern generator 7 and the output of the format convertor 190. The produced output of voltage values is supplied to the column drivers 80. The row selection pattern from the row selection pattern generator 7 is supplied also to row drivers 90. The column drivers 80 and the row drivers 90 drive column electrodes and row electrodes of a liquid crystal display pattern 40 based on the inputted signals. A driver control circuit 60 controls a driving timing to the column drivers 80 and the row drivers 90.
The driving circuit of the conventional liquid crystal display device as shown in FIG. 15 performs frame modulation before the data are stored in the memory 130, and a relatively simple circuit structure can be obtained. However, the memory 130 is required to have a read memory and a write memory which correspond two picture areas. Further, the VRAM used as the memory 130 is relatively expensive whereby the driving circuit can not be constituted economically. Further, the driving circuit have a problem that power consumption rate and radiation noise are relatively large because memory access is necessary at a high speed.